Electronic postage meters are well known. Such devices operate under microprocessor control to perform printing and accounting operations associated with the printing of a postal indicia on an envelope. In known meters such accounting may be carried out in a volatile memory and then transferred at a predetermined time to non-volatile memory for storage in the event that power is removed from the electronic postage meter. Alternatively, in other conventional meters all computations are carried out in battery-backed CMOS RAM non-volatile and there is no need for transfer from RAM in the event of power loss in the meter.
In these conventional electronic postage meters, each of the non-volatile memories used for storing the postal funds information must have both long retention times for the stored data, typically specified as approximately ten years for critical postage meter data, and a high endurance. Endurance is defined as the miximum number of times that a byte of data can be overwritten at a given address in memory. High endurance memories typically allow write operations of the order of 10,000 to 1,000,000 write cycles for a given byte. By contrast, low endurance memories typically allow write operation on the order of 10,000 or less.
Battery-backed RAMs work well, particularly in terms of endurance, but have the drawback that battery life which is critical for the retention of data is less than the life of the postage meter. Other nonvolatile memories such as the known MNOS devices are typically of low endurance, less than 10,000 write cycles. Devices such as the E.sup.2 PROM available from SEEQ Technology which combine high retention and high endurance of up to 1,000,000 write cycles are relatively expensive.
Various techniques have been used in conjunction with the lower endurance devices to overcome the handicap of limited write cycles while at the same time ensuring that critical accounting data is not lost either because the data has been corrupted in the memory or was improperly stored or improperly transferred to non-volatile memory.
U.S. Pat. No. 4,301,507 disclosed the real time accounting in RAM and storage in an MNOS memory only when power is removed from the meter. Eckert in U.S. Pat. No. 4,584,647 teaches a ring counter arrangement for storing counting data in a sequence of addresses in non-volatile memory from which postage value may be calculated based on the number of counts stored in the ring counter.
U.S. Pat. No. 4,706,215 of Kirschner et. al. discloses a postage meter having two non-volatile memories wherein data is stored in real time in one non-volatile memory and in a limited endurance memory on power-down.
U.S. application Ser. No. 292,194, filed Dec. 30, 1988 now U.S. Pat. No. 5,012,425 to Brown entitled ELECTRONIC POSTAGE METER HAVING AN IMPROVEMENT IN NONVOLATILE STORAGE OF ACCOUNTING DATA assigned to the Assignee of the instant application describes a redundant non-volatile memory arrangement comprising storage buffers in two-different types of non-volatile memory and in which postage meter register data may be updated or reconstructed on the basis of count data stored in a circular counter in a limited endurance device.
EPC Application No. 88104948 (Pub. No. 0285087) divides the postage meter accounting register information into high-weight and low-weight digit information and stores the lower weight digit information in a zone of the memory arranged as a circular storage area. The higher weight digit information is stored in a zone of the memory in conventional manner.
While these known techniques accomplish the result of enabling the use of a low endurance devices in the postage meter, each relies on a compromise between long retention and endurance.